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| XC2V250-5FGG256C资料 | |
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XC2V250-5FGG256C PDF Download |
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File Size : 105 KB
Manufacturer:XILINX Description:mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling edges of the internal system clock. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：XC2V250-5FGG256C 厂 家：XILINX 封 装：0749+ 批 号：35 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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