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| TP5088N资料 | |
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TP5088N PDF Download |
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File Size : 105 KB
Manufacturer:NS Description:Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) The 133-MHz core frequency supports 2:1 mode only. The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch and without conditional execution. 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) C Instruction cache is two-way, set-associative with 256 sets in 2 blocks C Data cache is two-way, set-associative with 256 sets C Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. C Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups Advanced on-chip emulation debug mode Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes the following: Improved operation, administration and maintenance (OAM) support OAM performance monitoring (PM) support Multiple APC priority levels available to support a range of traffic pace requirements Port-to-port switching capability without the need for RAM-based microcode Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability Optional statistical cell counters per PHY |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TP5088N 厂 家：NS 封 装：98+97+ 批 号：125 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
| MSN： |
| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
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