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| TL7705AIP资料 | |
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TL7705AIP PDF Download |
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File Size : 105 KB
Manufacturer:TI Description:The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB first as selected in the system register. The BCK frequency must be equal to or greater than 32 Fs for 16-bit data or 36 Fs for 18-bit data where Fs is the sample rate. Figure 2 illustrates the input timing. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TL7705AIP 厂 家：TI 封 装：99+ 批 号：31 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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