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| SRM2016C20资料 | |
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SRM2016C20 PDF Download |
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File Size : 105 KB
Manufacturer:SHARP Description:Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets PC100 SDRAM registered DIMM Specification Rev. 1.2 Distributes One Clock Input to One Bank of Ten Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input Separate Output Enable for Each Output Bank Operates at 3.3 V Vcc 125 MHz Maximum Frequency On-chip Series Damping Resistors Support Spread Spectrum Clock(SSC) Synthesizers ESD Protection Exceeds 3000 V per MIL-STD- 883, Method 3015 ; Exceeds 350 V Using MachineModel ( C = 200 pF, R = 0 ) Latch-Up Performance Exceeds 400 mA per JESD 17 Packaged in Plastic 24-Pin Thin Shrink Small- Outline Package |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SRM2016C20 厂 家：SHARP 封 装：95+ 批 号：1000 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
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| QQ：12230627,596815151,531081618 |
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