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| SNJ54LS85J资料 | |
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SNJ54LS85J PDF Download |
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File Size : 105 KB
Manufacturer:TI Description:At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6 performs 2 GFLOPS/666 MMACS 3M bit on-chip SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit in blocks 2 and 3) for simultaneous access by the core pro- cessor and DMA 4M bit on-chip mask-programmable ROM (2M bit in block 0 and 2M bit in block 1) Dual Data Address Generators (DAGs) with modulo and bit- reverse addressing Zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing Single Instruction Multiple Data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in busses and computational units allows sin- gle cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 5.4G bytes/s bandwidth at 333 MHz core instruction rate |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SNJ54LS85J 厂 家：TI 封 装：0550+ 批 号：1814 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
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| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
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