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| SNJ54LS30J资料 | |
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SNJ54LS30J PDF Download |
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File Size : 105 KB
Manufacturer:TI Description:One Instruction/Clock Execution Core Clock Rate is 2x the Bus Clock Load/Store Programming Model Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers (8 sets) Nine Addressing Modes User/Supervisor Protection Model Two-Way Set Associative Instruction Cache 80960JD - 4 Kbyte Programmable Cache Locking Mechanism Direct Mapped Data Cache 80960JD - 2 Kbyte Write Through Operation On-Chip Stack Frame Cache Seven Register Sets Can Be Saved Automatic Allocation on Call/Return 0-7 Frames Reserved for High-Priority Interrupts On-Chip Data RAM 1 Kbyte Critical Variable Storage Single-Cycle Access |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SNJ54LS30J 厂 家：TI 封 装：0918+ 批 号：190 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
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