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| SN74ALS580BN资料 | |
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SN74ALS580BN PDF Download |
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File Size : 105 KB
Manufacturer:TI Description: The MI-MV13 includes on-chip timing and control circuitry to control most of the pixel, ADC, and output multiplexing operations. However, the sensor still requires a controller (FPGA, CPLD, ASIC, etc.) to guide it through the full sequence of its operation. With the TrueSNAP freeze-frame electronic shutter signal charges are integrated in all pixels in parallel. The charges are then sampled into pixel analog memo- ries (one memory per pixel) and subsequently, row by row, are digitized and read out of the sensor. The inte- gration of photosignal is controlled by two control sig- nals: PG_N and TX_N. To clear pixels and start new integration, PG_N is made low. To transfer the data into pixel memory, TX_N is made low. The time differ- ence between the two procedures is the exposure time. It should be noted that neither the PG_N or TX_N pulses clear the pixel analog memory. Pixel memory can be cleared during the previous readout (i.e., the readout process resets the pixel analog memory), or by applying PG_N and TX_N together (i.e., clearing both pixel and pixel memory at the same time). With the TrueSNAP freeze-frame electronic shutter the sensor can operate in either simultaneous or sequential mode in which it generates continuous video output. In simultaneous mode, as a series of frames are being captured, the PG_N and TX_N signals are exercised while the previous frame is being read out of the sensor. In simultaneous mode typically the end of integration occurs in the last row of the frame (row #1023) or in the last row of the window of interest. The position of the start integration is then calculated from the desired integration time. In sequential mode the PG_N and TX_N signals are exercised to control the integration time, and then digitization and readout of the frame takes place. Alternatively, the sensor can run in single frame or snapshot mode in which one image is captured. The sensor has a column-parallel ADC architecture that allows the array of 1,280 analog-to-digital convert- ers on the chip to digitize simultaneously the analog data from an entire pixel row. The following input sig- nals are utilized to control the conversion and readout process: |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：SN74ALS580BN 厂 家：TI 封 装：00+ 批 号：21 数 量： 说 明： |
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