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| SN54S05J资料 | |
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SN54S05J PDF Download |
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File Size : 105 KB
Manufacturer:TI Description:Description Clock input. A[1:2] is the "true" side of the differential clock input. Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage for A[1:2]: 3.3V LVTTL VREF = 1650mV 2.5V LVTTL VREF = 1250mV Gate control for differential outputs Q1 and Q1 through Q5 and Q5. When G1 is LOW, the differential outputs are active. When G1 is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). Gate control for differential outputs Q6 and Q6 through Q10 and Q10. When G2 is LOW, the differential outputs are active. When G2 is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs disable HIGH. Clock outputs Complementary clock outputs Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1. Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3) Power supply for the device core and inputs Power supply return for all power No connect; recommended to connect to GND |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SN54S05J 厂 家：TI 封 装：0825+ 批 号：170 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
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