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| SN54LS241J资料 | |
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SN54LS241J PDF Download |
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File Size : 105 KB
Manufacturer:TI Description:Data inputs for a 8-bit bus. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. Data outputs for a 8-bit bus. Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF goes HIGH, and EF goes LOW. A Reset is required before an initial Write after power-up. Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable is asserted. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. Data will not be written into the FIFO if the FF is LOW. 3.3V volt power supply. Ground pin. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SN54LS241J 厂 家：TI 封 装：0824+ 批 号：1009 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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