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| SN54LS112AJ资料 | |
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SN54LS112AJ PDF Download |
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File Size : 105 KB
Manufacturer:TI Description:The first 2 bits accepted following the negative transition of the ENABLE input are interpreted as address If these ad- dress bits are not 1 1 no further information will be accept- ed from the DATA inputs and the internal data latches will not be changed when ENABLE returns high If these first 2 bits are 1 1 then all succeeding bits are ac- cepted as data and are shifted successively into the inter- nal shift register as long as ENABLE remains low Any data bits preceding the 20th to last bit will be shifted out and are thus irrelevant Data bits are counted as any bits following 2 valid (1 1) address bits with the ENABLE low When the ENABLE input returns high any further serial data input is inhibited Upon this positive transition of the ENABLE the data in the internal shift register is transferred into the internal data latches |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SN54LS112AJ 厂 家：TI 封 装：0916+ 批 号：290 数 量： 说 明： |
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