 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| SN54HC251J资料 | |
|
SN54HC251J PDF Download |
|
File Size : 105 KB
Manufacturer:MOT Description:With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/ CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R. |
|
| 相关型号 | |
| ◆ PXV1220S-3DB-N1 | |
| ◆ UF2492M388 | |
| ◆ Z86E0812PSC | |
| ◆ Z8622704PSC | |
| ◆ Z85C3008VSC | |
| ◆ Z8523010VSC | |
| ◆ Z84C9010VSC | |
| ◆ Z80SIO | |
| ◆ Z8028012VSC | |
| ◆ Z8018010VSC | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：SN54HC251J 厂 家：MOT 封 装：9636+ 批 号：4 数 量： 说 明： |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
| MSN： |
| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
建议使用分辨率:1024*768