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| SCC68681C1A44资料 | |
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SCC68681C1A44 PDF Download |
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File Size : 105 KB
Manufacturer:PH Description:an active LOW parallel enable (PE) input. When PE is LOW one set-up time prior to the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from serial data input (Ds), and the remaining bits are shifted one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the Ds input of the succeeding stage. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：SCC68681C1A44 厂 家：PH 封 装：04+ 批 号：117 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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