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| PS2002B资料 | |
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PS2002B PDF Download |
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File Size : 105 KB
Manufacturer:NEC Description:Synchronization. During interpolation, the chip accepts input data on alternate rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either held LOW or fed a square wave of half the CLK frequency, the part will continue to accept data on odd-numbered CLK edges and to stuff zeroes on even- numbered edges. Similarly, during decimation, the output data change only on alternate clock cycles. If the user operates SYNC as above, each even- numbered rising edge of CLK will trigger a change in the output. In all other modes, the state of SYNC doesnt affect operation of the chip. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：PS2002B 厂 家：NEC 封 装：94+ 批 号：113 数 量： 说 明： |
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