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| P8256AH资料 | |
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P8256AH PDF Download |
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File Size : 105 KB
Manufacturer:INTEL Description: Since this codecCfilter design has a single DAC architec- ture, the MCLK pin is used as the master clock for all analog signal processing including analogCtoCdigital conversion, digitalCtoCanalog conversion, and for transmit and receive fil- tering functions of this device. The clock frequency applied to the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de- vice has a prescaler that automatically determines the proper divide ratio to use for the MCLK input, which achieves the re- quired 256 kHz internal sequencing clock. The clocking re- quirements of the MCLK input are independent of the PCM data transfer mode (i.e., Long Frame Sync, Short Frame Sync, IDL mode, or GCI mode). |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：P8256AH 厂 家：INTEL 封 装：99+ 批 号：56 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
| MSN： |
| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
建议使用分辨率:1024*768