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| P3205资料 | |
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P3205 PDF Download |
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File Size : 105 KB
Manufacturer:INTEL Description:The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：P3205 厂 家：INTEL 封 装：00+ 批 号：495 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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