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| MSM82C53-2资料 | |
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MSM82C53-2 PDF Download |
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File Size : 105 KB
Manufacturer:OKI Description: The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. Accesses begin with the registra- tion of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits regis- tered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0CA11 select the row). The address bits registered coincident with the READ or WRITE com- mand are used to select the starting column location for the burst access. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：MSM82C53-2 厂 家：OKI 封 装：04+ 批 号：650 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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