 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| M54532P资料 | |
|
M54532P PDF Download |
|
File Size : 105 KB
Manufacturer:MIT Description:Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 3) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting |
|
| 相关型号 | |
| ◆ PXV1220S-3DB-N1 | |
| ◆ UF2492M388 | |
| ◆ Z86E0812PSC | |
| ◆ Z8622704PSC | |
| ◆ Z85C3008VSC | |
| ◆ Z8523010VSC | |
| ◆ Z84C9010VSC | |
| ◆ Z80SIO | |
| ◆ Z8028012VSC | |
| ◆ Z8018010VSC | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：M54532P 厂 家：MIT 封 装：00+ 批 号：67 数 量： 说 明： |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
| MSN： |
| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
