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| M53206P资料 | |
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M53206P PDF Download |
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File Size : 105 KB
Manufacturer:MIT Description:After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1Cwire reset the DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2 µs O2/BSY2 is driven low. Both outputs will remain low until the communication on the I/O line is finished. A busy signal for a bit time slot differs from the reset busy signal only in that both O1/BSY1 and O2/BSY2 are driven low immediately. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：M53206P 厂 家：MIT 封 装：98+ 批 号：39 数 量： 说 明： |
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