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| LT1573CS8资料 | |
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LT1573CS8 PDF Download |
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File Size : 105 KB
Manufacturer:LT Description:NOTES 15After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s. 16These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV DD + 30 mV or go more negative than AGND C 30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 17For higher gains (8) at f CLK IN = 2.4576 MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0. 18When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV DD current and power dissipation will vary depending on the crystal or resonator type (see Clocking and Oscillator Circuit section). 19Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz. 20PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ. 21If the external master clock continues to run in standby mode, the standby current increases to 150 µA typical with 5 V supplies and 75 µA typical with 3.3 V supplies. When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator type (see Standby Mode section). Specifications subject to change without notice. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：LT1573CS8 厂 家：LT 封 装：0106+ 批 号：158 数 量： 说 明： |
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