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| LM161J/883QS资料 | |
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LM161J/883QS PDF Download |
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File Size : 105 KB
Manufacturer:NS Description:During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD ( 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor: td = 2.1 104 CT Where CT is in farads td is in seconds |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：LM161J/883QS 厂 家：NS 封 装：97+ 批 号：10 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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