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| K3953D资料 | |
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K3953D PDF Download |
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File Size : 105 KB
Manufacturer:EPCOS Description:Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：K3953D 厂 家：EPCOS 封 装： 批 号：1390 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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