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| IDT7132SA55J资料 | |
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IDT7132SA55J PDF Download |
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File Size : 105 KB
Manufacturer:IDT Description:The K9K1208U0A has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: col- umn address, low row address and high row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K1208U0A. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：IDT7132SA55J 厂 家：IDT 封 装：99+/00+ 批 号：21 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
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