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| DG333ADW资料 | |
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DG333ADW PDF Download |
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File Size : 105 KB
Manufacturer:VISHAY Description:When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1 and WEN2/LD are held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4261/71/81/91V has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：DG333ADW 厂 家：VISHAY 封 装：01+ 批 号：164 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
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