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| CY7C60123-PVXC资料 | |
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CY7C60123-PVXC PDF Download |
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File Size : 105 KB
Manufacturer:CY Description: In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：CY7C60123-PVXC 厂 家：CY 封 装：05+ 批 号：1 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
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| QQ：12230627,596815151,531081618 |
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| 公司地址： 上海市古楼公路348弄25号 |
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