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| ATTINY26-8SI资料 | |
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ATTINY26-8SI PDF Download |
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File Size : 105 KB
Manufacturer:AT Description:Function Clock source selection 0: clocks pass PLL, use XIN (pin 12) 1: bypass PLL, use CLKIN (pin 11) External clock source; bypass PLL Crystal oscillator in, or external clock in; if external clocks used, leave Xout (pin 13) unconnected Crystal oscillator out Pixel clock output Output enable. 0: enable, 1: disable LSB of SIF slave address SIF master/slave selection. 0: slave, 1: master SIF clock SIF data Power down control, 0: power down, 1: active Resistor to ground = 25 KΩ @ 48 MHz main clock, (or 50KΩ @ 24 MHz main clock) Chip reset, active low Data output bit 10 Data output bit 9 Data output bit 8 Data output bit 7 Data output bit 6; if pulled up/down, the initial value of TIMING_CONTROL_LOW[2] (VSYNC polarity) is 1/0 Data output bit 5; if pulled up/down, the initial value of TIMING_CONTROL_LOW[1] (HSYNC polarity) is 1/0 Data output bit 4; if pulled up/down, the initial value of AD_IDL[3] (Sub ID) is 1/0 Data output bit 3; if pulled up/down, the initial value of AD_IDL[2] (Sub ID) is 1/0 Data output bit 2; if pulled up/down, the initial value of AD_IDL[1] (Sub ID) is 1/0 Data output bit 1; if pulled up/down, the initial value of AD_IDL[0] (Sub ID) is 1/0 Data output bit 0; if pulled up/down, the synchronization mode is in master/slave mode which requires HSYNC and VSYNC operating in output/input mode Horizontal sync signal Vertical sync signal Flash light control Analog ramp output Sensor analog power Sensor analog ground Sensor digital power Sensor digital ground Digital power |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 号：ATTINY26-8SI 厂 家：AT 封 装：03+ 批 号：951 数 量： 说 明： |
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