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| AT29C512-12PC资料 | |
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AT29C512-12PC PDF Download |
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File Size : 105 KB
Manufacturer:AT Description:Functional Description The AT29C512-12PC is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or 2 of the input frequency. The FSELA, FSELB, FSELC, FSELD and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the the 2 outputs. For the functionality of the MR control input, see Figure 5. , Functional Diagram, on page 7. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The AT29C512-12PC can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the AT29C512-12PC supports positive (PECL) and negative (ECL) supplies. The AT29C512-12PC is pin and function compatible to the MC100EP222. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：AT29C512-12PC 厂 家：AT 封 装：98+ 批 号：66 数 量： 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
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| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
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