 |
|||||||
|
|||||||
|
|
|||||||
|
|||||||
|
|
| ADG508AKP资料 | |
|
ADG508AKP PDF Download |
|
File Size : 105 KB
Manufacturer:AD Description:Clock input. CLKIN provides the clock signal to be distributed by the ADG508AKP clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the output signal. CLKIN must have a fixed frequency and phase in order for the PLL to acquire lock. Once the circuit is powered up and a valid signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to CLKIN. |
|
| 相关型号 | |
| ◆ PXV1220S-3DB-N1 | |
| ◆ UF2492M388 | |
| ◆ Z86E0812PSC | |
| ◆ Z8622704PSC | |
| ◆ Z85C3008VSC | |
| ◆ Z8523010VSC | |
| ◆ Z84C9010VSC | |
| ◆ Z80SIO | |
| ◆ Z8028012VSC | |
| ◆ Z8018010VSC | |
| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
|
型 号：ADG508AKP 厂 家：AD 封 装：92+ 批 号：92 数 量： 说 明： |
|||||
|
运 费： 所在地： 新旧程度： |
|||||
| 联系人：张小姐、 颜先生13661569158 |
| 电 话：400-878-9158,021-54286636 |
| 手 机：13661569158 |
| QQ：12230627,596815151,531081618 |
| MSN： |
| 传 真：021-54286636 |
| EMail：susumu@susumu.com.cn |
| 公司地址： 上海市古楼公路348弄25号 |
建议使用分辨率:1024*768